1. Field of the Invention
The present invention relates to a stacked semiconductor device wherein a plurality of different or identical chips are stacked using through-hole electrodes, and more particularly to a method of testing continuity between an internal terminal in each chip and an external terminal.
2. Description of the Related Art
In recent years, semiconductor packages wherein a plurality of chips are stacked using through-hole electrodes have been developed (see, for example, JP2002-305283A).
FIG. 1 illustrates an exemplary configuration of a semiconductor package wherein a plurality of memory core chips and an interposer chip are stacked together.
A signal which is applied to external terminal 5 is transmitted to each memory core chip 2 through through-hole electrodes 4 and internal terminal junctions 3. For this reason, it is necessary to ensure that the connection status of neighboring chips at internal terminal junctions 3 is good.
In a semiconductor package wherein a plurality of chips are stacked for assembly, it is desirable to conduct a test to determine whether or not there are any defects in the connection between chips prior to testing the operation of the circuits in each chip. By conducting a test of connection between chips beforehand, it is possible to detect and exclude a package having assembly defect(s). This enables a more efficient test of the operation of the circuits to be subsequently conducted.
Heretofore, a test to determine whether or not there is continuity between an internal terminal in each chip an external terminal of a package is conducted in such a way that a diode element which is intended to protect against ESD (electrostatic destruction) and which is connected between GND (ground terminal) and an external terminal is used and a voltage is applied across the diode element which causes current to flow through the diode element.
A description will now be given for a conventional method of conducting a test to determine whether or not an internal terminal in each memory core chip 2 is connected with external terminal 5 through internal terminal junction 3, through-hole electrode 4 and interposer chip 1 in the stacked semiconductor device shown in FIG. 1. Here, a check to determine whether or not internal terminal junctions 3, which are generated when stacking chips, are connected in a secure manner, is also carried out.
FIG. 2 illustrates the detailed configuration of an input/output section of a stacked semiconductor device of the related art. This semiconductor device includes interposer chip 1, 14 memory core chips 2a, 2b, . . . , 2n which are stacked one above another, and external terminals 5-1, 5-2, and 5-3. Neighboring chips are connected one above another by through-hole electrodes (not referenced in FIG. 2) and internal terminal junctions 3ab, 3mn. Memory core chip 2a includes internal circuit 20a, input circuits 11a1 and 11a2, data input/output circuit 12a, internal terminals 13a1, 13a2, 13a3, and diode elements 14a1, 14a2, 14a3. Similarly, memory core chip 2b includes internal circuit 20b, input circuits 11b1, 11b2, data input/output circuit 12b, internal terminals 13b1, 13b2, 13b3, and diode elements 14b1, 14b2, 14b3. Memory core chip 2n includes internal circuit 20n, input circuits 11n1 and 11n2, data input/output circuit 12n, internal terminals 13n1, 13n2, 3n3, and diode elements 14n1, 14n2, 14n3. The through-hole electrodes in each memory core chip are connected with internal terminals 13a1, 13a2, . . . , 13n3 in each chip. Diode elements 14a1, 14a2, . . . , 14n3 are the aforementioned diode which is intended to protect against ESD. Each through-hole electrode is electrically connected with corresponding external terminals 5-1, 5-2 and 5-3. In FIG. 2, an external terminal and a through-hole electrode for GND terminal are not shown.
A description is made of conducting a test to determine whether or not there is continuity between an external terminal and a corresponding internal terminal in each chip in the stacked semiconductor device. First, 0 (volt) is applied to GND terminal and a minus level voltage (for example −1 Volt) is applied to external terminal 5-1. That is, a test is made to determine whether or not there is continuity between external terminal 5-1, internal terminal 13a1 in memory core chip 2a, internal terminal 13b1 in memory core chip 2b, . . . , and internal terminal 13n1 in memory core chip 2n. Next, the value of current generated between external terminal 5-1 and GND terminal is measured. The value of current that is measured is herein the total of the value of current flowing through diode element 14a1, the value of current flowing through diode element 14b1, . . . , and the value of current flowing through diode element 14n1. If all memory core chips 2a, 2b, . . . , and 2n are connected one above another properly, the value of current that is measured should be 14 times the value of current flowing through diode element 14a1. However, if, for example, internal terminal junction 3ab has any trouble and is incompletely connected between memory core chips 2a and 2b, then only the value of current flowing through diode element 14a1 in memory core chip 2a is measured. Furthermore, if an internal terminal junction which has caused a problem is internal terminal junction 3mn, for example, then the total value of current flowing through the diodes except for diode element 14n1 is measured. In the latter case, the total value of current measured is approximate to the total value of current when all the internal terminal junctions are connected to outer terminal 5-1. The same applies to internal terminals 13a2, 13b2, . . . , 13n2 to be connected to outer terminal 5-2, and to internal terminals 13a3, 13b3, . . . , 13n3 to be connected to outer terminal 5-3.
In addition, the states of all the internal terminal junctions are not always the same. Some internal terminal junctions may have their resistance values greater than the expected value. Resistance values of the internal terminal junctions are thus not a fixed value. In this case, the value of current to be measured is not always an integral multiple of the value of current flowing through one diode element.
JP2006-120812A discloses a semiconductor device having a plurality of stacked chips wherein at the time of normal operation, test stabs are disconnected from main signal wirings to thereby improve the quality of signals during normal operation.
As described above, in a semiconductor device having identical chips which are stacked using through-electrodes, corresponding input terminals in each chip are all connected in series with one above another. Therefore, if a test to determine whether or not there are defects in the connection between chips is conducted in the aforementioned manner, then current flows through all the diode elements connected with GND terminal. As a result, even if a chip having a defective connection is present, it is difficult to identify the chip having a defective connection.
Also, in a semiconductor device having different chips which are stacked, an internal terminal junction to communicate with signals between the neighboring chips does not correspond to an external terminal. Therefore, a continuity test cannot be conducted because the internal terminal junction cannot be seen as the external terminal. As a result, whether or not there are defects in the connection between chips cannot be seen until a test to determine whether or not the circuits in a semiconductor package operate properly, is conducted, and cannot be easily found prior to testing the operation of the circuits.